1. Field of the Invention
The present invention relates to an Electrically Erasable and Programmable ROM read only memory (EEPROM), and more particularly to an EEPROM circuit in which the write operation of data can be continuously performed without the erase operation, a memory device having an EEPROM circuit, and an IC card having an EEPROM circuit.
2. Description of the Related Art
An EEPROM circuit and an EPROM circuit both have a plurality of nonvolatile memory cell transistors arranged in rows and columns. Each memory cell transistor can be switched between two distinct states (i.e., bi-stable states). Depending on the two distinct states, each of the memory cell transistors stores 1-bit data of "0 (logic low)" or "1 (logic high)". The EEPROM circuit and the EPROM circuit are of the same type in that both circuits are read only memories (ROMs) capable of rewriting data. However, the EEPROM circuit can electrically erase data, while the EPROM circuit erases data with ultraviolet radiation or the like. At least in this respect, the EEPROM circuit and the EPROM circuit are greatly different from each other.
Hereinafter, in this specification, the "written state" of a memory cell or a memory cell transistor indicates the state in which the threshold voltage of the memory cell transistor is smaller than a specific value (for example, about 1 volt (V)). This "written state" is represented as "0". On the other hand, the "erased state" of the memory cell or the memory cell transistor indicates a state in which the threshold voltage is larger than the specific value. This "erased state" is represented as "1". Further, the phrase "to write data" means that the memory cell or memory cell transistor is put into the "written state (0)", and "to erase data" means that the memory cell or the memory cell transistor is put into the "erased state (1)".
In a memory cell transistor in the written state, when a potential higher than the threshold voltage (for example, about 0 V or more) is applied to the gate electrode thereof, the source and the drain of the memory cell transistor are electrically connected to each other. Due to such electrical continuity, the "written state (0)" corresponds to the "ON state" of the memory cell transistor. On the other hand, the memory cell transistor in the erased state has a high threshold voltage. Accordingly, the source and the drain of the memory cell transistor are not electrically connected to each other, even when a voltage in the range of about 5 V to 10 V is applied to the gate electrode thereof. Accordingly, the "erased state (1)" corresponds to the "OFF state" of the memory cell transistor.
In the EEPROM circuit, the operation for "writing data" is performed, for example, for every 1 byte. In this case, respective 8 memory cells are put into the "written state (0)" or the "erased state (1)", in accordance with the contents of data to be written. In the EEPROM circuit, first of all, the memory cells are all put into the "erased state (1)" (data is erased), before such a write operation. Then, after erasing data, the states of the selected memory cells from the 8 memory cells are changed to the "written state (0)", and the states of the non-selected memory cells remain the "erased state (1)". Which memory cells should be selected is determined by the electrical potentials on bit lines connected to the respective memory cells.
In the case where 8 memory cells store 8-bits of data such as {11111100}, the change of the data from {111111100}, for example, to {11111000}, will be done as follows. In this example case, the states of the 8 memory cells of {11111100} are first changed to {11111111} by the erase operation, and then to {11111000} by the write operation.
On the contrary, in the EPROM circuit, data erasing is achieved by ultraviolet radiation or the like, and the operation for "erasing data" is not performed before the operation for "writing data". In the EPROM circuit, new data can be stored by repeating the operation for "writing data". In the case where 8 memory cell transistors store 8-bits of data such as {11111100}, the change of the data from {111111100} to {11111000}, will be done as follows. In this example case, the states of the 8 memory cells of {11111100} are directly changed to {11111000} by the write operation. Such a rewrite of 8-bit data is accomplished by "writing data" only to the memory cell transistor at the third bit (the third memory cell transistor from the right end).
In the EPROM circuit, the change (1.fwdarw.0) from the erased state (1) to the written state (0) is electrically achieved; however, the change (0.fwdarw.1) from the written state (0) to the erased state (1) cannot be electrically achieved. Therefore, in the case of electrically rewriting data, the written state (0) cannot be changed to the erased state (1) by mistake. Thus, regarding the protection of data, the EPROM circuit is superior to the EEPROM circuit.
The structure and the operation of a conventional EEPROM circuit will be described with reference to FIG. 9. The shown EEPROM circuit has a plurality of nonvolatile memory cell transistors arranged in rows and columns. For simplicity, only memory cell transistors MT1 to MTn disposed in a single column and n rows are shown in FIG. 9. In this specification, a series of the memory cells parallel to a word line WL is referred to as a "column" of the memory cells, and a series of the memory cells parallel to bit lines BL1 to BLn is referred to as a "row" of the memory cells.
Each of the nonvolatile memory cell transistors MT1 to MTn has a gate electrode G, a drain electrode D and a source electrode S. The drain electrodes D of the nonvolatile memory cell transistors MT1 to MTn are connected to the bit lines BL1 to BLn, respectively, via transistors MS1 to MSn. When the electrical potential of the word line WL is at a high level, the drain electrodes D of the memory cell transistors MT1 to MTn are each electrically connected to the bit lines BL1 to BLn by the transistors MS1 to MSn; and when the electrical potential of the word line WL is at a low level, the drain electrodes D of the memory cell transistors MT1 to MTn are not connected to the bit lines BL1 to BLn. Each of the bit lines BL1 to BLn is connected to a row decoder and the like (not shown). The electrical potential of each bit line BLi (i is an integer from 1 to n) varies to a high level or to a low level. Which bit lines BLi should have a high-level electrical potential is dependent on the contents of data to be written (DATA).
The source electrodes S of the nonvolatile memory cell transistors MT1 to MTn are grounded via a single transistor TR. The source electrodes S are grounded or put in an open state by the transistor TR in response to a control signal.
The gate electrodes G of the nonvolatile memory cell transistors MT1 to MTn are connected to a page line PL via a transistor SG. When the electrical potential of the word line WL is at a high level, the gate electrodes G are electrically connected to the page line PL via the transistor SG, and when the electrical potential of the word line WL is at a low level, the gate electrodes G are not electrically connected to the page line PL.
In such conventional EEPROM circuits, data writing is achieved as follows.
A1. Erase Operation:
The electrical potentials of the selected word line WL, page line PL and bit lines BL1 to BLn are set at a high level, a high level and a low level, respectively. The source electrodes S of the memory cell transistors MT1 to MTn are put in an open state. In this case, the electrical potentials of the gate electrodes G of the memory cell transistors MT1 to MTn become high, according to the electrical potential of the page line PL. The electrical potentials of the drain electrodes D of the memory cell transistors MT1 to MTn become low, according to the electrical potentials of the bit lines BL1 to BLn. The electrons from the drain electrodes D are injected into floating gate electrodes (not shown) of the memory cell transistors by the electric fields generated between the gate electrodes G and the drain electrodes D. As a result, the threshold voltages of the memory cell transistors are raised. The erase operation is always performed before the write operation which will be described below.
B1. Write Operation:
After performing the above-mentioned erase operation, the electrical potentials of the selected word line WL and the page line PL are set at a high level and a low level, respectively. The source electrodes S of the memory cell transistors MT1 to MTn are put in an open state by a second control signal. The electrical potential of the bit line BLi is set at a high level, the bit line BLi being connected to the drain electrode D of the memory cell transistor MTi into which data will be written, selected from the plurality of memory cell transistors MT1 to MTn belonging to the selected row.
In this case, the electrical potentials of the gate electrodes G of the memory cell transistors MT1 to MTn are all set at a low level, according to the electrical potential of the page line PL. The electrical potentials of the drain electrodes D of the memory cell transistors MT1 to MTn are set at a high level or a low level, according to the electrical potentials of the corresponding bit lines BL1 to BLn. The electrons are released from the floating gate electrode (not shown) of the memory cell transistor MTi to the drain electrode D thereof by the electric field generated between the drain electrode D connected to the bit line BLi having a high-level electrical potential and the gate electrode G. As a result, the threshold voltage of the memory cell transistor MTi is lowered.
In the above-mentioned prior art technique, the following problem arises.
In the conventional EEPROM circuit, the erase operation of data is always performed before the write operation of data. Due to this erase operation, the data may be electrically erased by mistake (erroneous erase). Accordingly, if the write operation can be continuously performed without the erase operation, the erroneous erase can be avoided.
However, if the write operation of data is continuously performed in the conventional EEPROM circuit, the following problem arises.
The problem will be described with reference to FIG. 9. For example, the memory cell transistor MT1 is in the erased state (1), and the memory cell transistor MT2 is in the written state (0). Next, data is written into the memory cell transistor MT1, while no data is written into the memory cell transistor MT2.
In this case, it is necessary that the electrical potentials of the gate electrode G and the drain electrode D of the memory cell transistor MT1 are set at a low level and a high level, respectively, and the source electrode S thereof is put in an open state. On the other hand, it is also necessary that the electrical potentials of the gate electrode G and the drain electrode D of the memory cell transistor MT2 are both set at a low level, and the source electrode S thereof is put in an open state. However, since the threshold voltage of the memory cell transistor MT2 is low, the current is leaked between the drain electrode D and the source electrode S of the memory cell transistor MT2, even if the electrical potential of the drain electrode D of the memory cell transistor MT1 is at a low level. That is, a leak path is formed between the source electrode S and the drain electrode D of the memory cell transistor MT2 into which data is written. In addition, the source electrodes S of the memory cell transistors MT1 to MTn are connected to each other, so that the source electrode S of the memory cell transistor MT1 is also connected to the bit line BL2 having a low-level electrical potential, via the leak path of the memory cell transistor MT2. Therefore, the source electrode S of the memory cell transistor MT1 is no longer open. As a result, data cannot be written into the memory cell transistor MT1.